VHDL

Files

File	Description	Synthesis possible
detectClock.zip 3kB	Detects a clock running on normal (not clock) input pin (with Testbench) This works, but in general you should avoid designs where you have to use such constructions! Format: Zipped VHDL Entity (detectClock.vhd, TB_detectClock.vhd) Copyright: Klaus Ruzicka, 1999	yes
PRBS.zip 3kB	Synthesiseable PRBS Generator Generate pseudo random sequences with a pattern trigger output; Pattern: (01 and PRBS=2^n-1, n=7,9,11,15,20,23,31); Speed: max 210MHz on Actel 42MX (see picture) Format: Zipped VHDL Entity (PRBS.vhd) Copyright: Klaus Ruzicka, 2001	yes
pSync.zip 2kB	Synchronise (short) pulses between different clock domains (with Testbench) This works, but in general you should avoid designs where you have to use such constructions! Format: Zipped VHDL Entity (pSync.vhd, TB_pSync.vhd) Copyright: Klaus Ruzicka, 1999	yes
stream.zip 4kB	Bit Stream / PRBS Generator for TestBenches Bit Stream defined by an external textfile; Pattern: (PRBS=2^n-1, n=7,9) Format: Zipped (getStream.vhd, RLLstream.txt,TB_getStream.vhd) Copyright: Klaus Ruzicka, 1999	NO
stringfkt.zip 4kB	A set of some useful (String) functions to enhance the textoutput routines for testbenches (not for synthesis) Contents: Integer=>String, String(constant)=>String, std_logic=>char, std_logic_vector=>String(hex/binary/bcd/decimal), std_logic_vector(binary offset/2th complement)=>String(signed decimal), string(vv.nnnnnnnE+mmm)=>string(Integer), string(Integer)=>std_logic_vector, std_logic_vector: binary offset<=>2th complement. Format: Zipped VHDL Package (strfkt.vhd) Copyright: Klaus Ruzicka, 2001	NO
VHDLhlp.zip 182kB	VHDL Language Reference (VHDL 87 and VHDL 93) Format: Zipped Windows Help File (VHDL.hlp) Copyright: Aldec Inc., 1997	N/A

Books

Title	Author(s)	Publisher	Year	ISBN	Language
The Designers Guide to VHDL	Peter J. Ashenden, Wayne Wolf	Morgan Kaufmann	2nd ed. 2002	1-55-860674-2
The VHDL Reference	Heinkel, Padeffke, Haas, Buerner, Braisz, Gentner, Grassmann	Wiley	1999	0-47-189972-0
VHDL for Designers	Sjoholm, Lindh	Prentice Hall	1997	0-13-473414-9
VHDL Made Easy!	Pellerin, Taylor	Prentice Hall	1997	0-13-650763-8
VHDL Synthese	Reichardt, Schwarz	Oldenburg	1997	3-48-625128-7

Other Information Sources (Links)

• Ben Cohen's VHDL page
• Informatik: Uni Hamburg
• Newsgroup: comp.lang.vhdl          via http://www.deja.com
• VHDL Online (/)
• Accellera (früher VHDL.org)
• FreeHDL Project (Simulator+Frontend+WaveformViewer)

more VHDL stuff (may miss due to disk space restrictions)

back to my index-page

laus Ruzicka

last update: 9.10.2001